Synopsys jobs - San Jose, CA
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| Dec 25 | DFT ASIC Engineer | Alchemy Search Partners | San Jose, CA |
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test using state of the art EDA tools (Synopsys, Mentor , LogicVison, Syntest). Knowledge of tcl scripting language, Magma synthesis tool. Experience Desired: Requirements:... more |
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| Dec 24 | DFT ASIC Engineer | Alchemy Search Partners | San Jose, CA |
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test using state of the art EDA tools (Synopsys, Mentor , LogicVison, Syntest). Knowledge of tcl scripting language, Magma synthesis tool. Experience Desired: Requirements:... more |
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| Dec 22 | Physical Design Engineer | Buxton Consulting | Sunnyvale, CA |
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Cadence tools like SoCE, Voltage Storm, Synopsys tools like ICC, Prime Time, Star RC, Synopsys DC, Mentor tools like Calibre for DRC, LVS etc a must. Email to a friend... more |
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| Dec 22 | CAD Manager | Terran Systems | Mountain View, CA |
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with Cadence, Mentor Graphics, Agilent, Synopsys Tools Required Experience: Minimum 5 years in a similar CAD position with and IC design company Minimum of BSEE or equivalent... more |
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| Dec 21 | SENIOR PHYSICAL DESIGN ENGINEER | PLX Technology | Sunnyvale, CA |
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o Hands on experience with Magma, Synopsys and/or Cadence back end tools. o Proficient in script writing: Perl, TCL, Linux/Unix shell scripts. o Proficiency in analyzing reports... more |
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| Dec 20 | VLSI FULL CHIP INTEGRATION & PHYS DESIGN VERIFICATION ENG. | NVIDIA | Santa Clara, CA |
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g DRC & LVS debugging a must. - Fullchip tapeout experience highly desired. - Experience with at least one VLSI verification flow needed: Synopsys Hercules, Magma Quartz, or... more |
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| Dec 19 | Verification Applications Engineer | CAE Recruiters | San Jose, CA |
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?Experience with Verilog simulation Synopsys DesignCompiler, Synopsys PrimeTime, perl, TCL and UNIX shell scripting ?Working knowledge of VHDL, SystemVerilog, Specman, Vera,... more |
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| Dec 19 | High Speed : CPU Designer | Modicom | San Jose, CA |
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the entire ASIC design cycle (Verilog, Synopsys Design Compiler, Prime Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). --Should be proficient... more |
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| Dec 19 | SENIOR PHYSICAL DESIGN ENGINEER | PLX Technology | Sunnyvale, CA |
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o Hands on experience with Magma, Synopsys and/or Cadence back end tools. o Proficient in script writing: Perl, TCL, Linux/Unix shell scripts. o Proficiency in analyzing reports... more |
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| Dec 18 | Sr. CAE II | Synopsys | Mountain View, CA |
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technical and marketing support for Synopsys DesignWare Intellectual Property ... direct technical customer support for Synopsys? IP products in order to supply... more |
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| Dec 18 | High Speed : CPU Designer | Modicom | San Jose, CA |
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the entire ASIC design cycle (Verilog, Synopsys Design Compiler, Prime Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). --Should be proficient... more |
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| Dec 18 | ASIC Design Engineer | Slac National Accelerator Laboratory | Menlo Park, CA |
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software such as Tanner, Cadence, Mentor, Synopsys is required. Experience writing and simulating VHDL or Verilog code with subsequent synthesis is desired. Experience in... more |
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| Dec 18 | ASIC Design Engineer, #35186 | Slac National Accelerator Laboratory | Menlo Park, CA |
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software such as Tanner, Cadence, Mentor, Synopsys is required. Experience writing and simulating VHDL or Verilog code with subsequent synthesis is desired. Experience in... more |
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| Dec 18 | Hardware Engineer | Sun Microsystems | Santa Clara, CA |
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Exposure to Cadence/Synopsys tool capabilities in analysis of custom circuits. Understanding of basic power estimation and modeling for SRAMs and Register files. Knowledge of... more |
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| Dec 17 | SAP Technical Analyst | Synopsys | Mountain View, CA |
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send resume, indicating Req# 9463, to: Synopsys, Inc., Attn: HR Resumes, 700 E. ... View, CA 94043-4033; E-mail: careers@synopsys.com (ASCII textonly, no attachments... more |
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| Dec 17 | Employee Communications Manager | Synopsys | Mountain View, CA |
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motivational communications with Synopsys global employees. While the focus ... in semiconductor design and manufacturing. Synopsys' comprehensive, integrated... more |
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| Dec 17 | Verification Applications Engineer | CAE Recruiters | San Jose, CA |
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?Experience with Verilog simulation Synopsys DesignCompiler, Synopsys PrimeTime, perl, TCL and UNIX shell scripting ?Working knowledge of VHDL, SystemVerilog, Specman, Vera,... more |
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| Dec 17 | Physical design opportunity | Synapse Design Automation | San Jose, CA |
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or engineering MUST have experience using Synopsys ICC / Magma DP for ... atleast one complex chip (10M gates) using Synopsys IC compiler tool. Knowledge of low... more |
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| Dec 17 | Senior Engineer, ASIC Design | Marvell | Santa Clara, CA |
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in ASIC design development using CAD tools (Synopsys flow preferred). (MSEE counts as 2 years experience.) Description: Perform various design tasks for system-on-chip (SoC)... more |
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| Dec 17 | Engineer, Staff Design | Marvell Semiconductor | Santa Clara, CA |
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Working knowledge of Verilog, Verilog AMS Synopsys DC-Compiler, Primetime, Matlab, C, System C, PLI and PERL. Working knowledge of Verilog XL, NC-Verilog or VCS, SPICE and HSIM. more |
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| Dec 16 | Principle Design Engineer: | GDA Technologies | San Jose, CA |
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& DFT (design for testability) using Synopsys & Mentor Graphics tools; post silicon verification; Static timing analysis using Prime Time tool; Place & route using Cadence First... more |
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| Dec 16 | Member of Technical Staff, IC Physical Designs: | GDA Technologies | San Jose, CA |
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complete ASIC physical design flow using - Synopsys, - Cadence, & - Magma tools Full chip assembly & tape-out to foundry; PERL, TCL, & TK scripting languages. Desired Attributes... more |
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| Dec 16 | Member of Technical Staff, ASIC Design: | GDA Technologies | San Jose, CA |
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complete ASIC physical design flow using - Synopsys, - Cadence, & - Magma tools Fullchip assembly & tapeout to foundry; PERL, TCL, & TK scripting languages. Desired Attributes... more |
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| Dec 16 | Sr. Technical Trainer (ASIC Design Service Group) | GDA Technologies | San Jose, CA |
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such as - Synplicity's Amplify ASIC, - Synopsys' Physical Compiler and PrimeTime, - Magmas' Blast Fusion; Provide training using EDA tools such as - NC-Verilog, VCS, - Modelsim,... more |
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| Dec 16 | Hardware Engineer | Sun Microsystems | Santa Clara, CA |
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Exposure to Cadence/Synopsys tool capabilities in analysis of custom circuits. Understanding of basic power estimation and modeling for SRAMs and Register files. Knowledge of... more |
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